? 2000 fairchild semiconductor corporation ds006368 www.fairchildsemi.com june 1986 revised march 2000 DM74LS109a dual positive-edge-triggered j-k flip-flop with preset, clear, and complementary outputs DM74LS109a dual positive-edge-triggered j-k flip-flop with preset, clear, and complementary outputs general description this device contains two independent positive-edge-trig- gered j-k flip-flops with complementary outputs. the j and k data is accepted by the flip-flop on the rising edge of the clock pulse. the triggering occurs at a voltage level and is not directly related to the transition time of the rising edge of the clock. the data on the j and k inputs may be changed while the clock is high or low as long as setup and hold times are not violated. a low logic level on the preset or clear inputs will set or reset the outputs regard- less of the logic levels of the other inputs. ordering code: devices also available in tape and reel. specify by appending the suffix letter x to the ordering code. connection diagram function table h = high logic level l = low logic level x = either low or high logic level - = rising edge of pulse q 0 = the output logic level of q before the indicated input conditions were established. toggle = each output changes to the complement of its previous level on each active transition of the clock pulse. note 1: this configuration is nonstable; that is, it will not persist when pre- set and/or clear inputs return to their inactive (high) state. order number package number package description DM74LS109am m16a 16-lead small outline integrated circuit (soic), jedec ms-012, 0.150 narrow DM74LS109an n16e 16-lead plastic dual-in-line package (pdip), jedec ms-001, 0.300 wide inputs outputs pr clr clk j k qq lhxxx h l hl xxx l h l l x x x h (note 1) h (note 1) hh - ll l h hh - h l toggle hh - lh q 0 q 0 hh - hh h l hh lxx q 0 q 0
www.fairchildsemi.com 2 DM74LS109a absolute maximum ratings (note 2) note 2: the absolute maximum ratings are those values beyond which the safety of the device cannot be guaranteed. the device should not be operated at these limits. the parametric values defined in the electrical characteristics tables are not guaranteed at the absolute maximum ratings. the recommended operating conditions table will define the conditions for actual device operation. recommended operating conditions note 3: c l = 15 pf, r l = 2 k w , t a = 25 c and v cc = 5v. note 4: c l = 50 pf, r l = 2 k w , t a = 25 c and v cc = 5v. note 5: the symbol ( - ) indicates the rising edge of the clock pulse is used for reference. note 6: t a = 25 c and v cc = 5v. supply voltage 7v input voltage 7v operating free air temperature range 0 c to + 70 c storage temperature range - 65 c to + 150 c symbol parameter min nom max units v cc supply voltage 4.75 5 5.25 v v ih high level input voltage 2 v v il low level input voltage 0.8 v i oh high level output current - 0.4 ma i ol low level output current 8 ma f clk clock frequency (note 3) 0 25 mhz f clk clock frequency (note 4) 0 20 mhz t w pulse width clock high 18 (note 3) preset low 15 ns clear low 15 t w pulse width clock high 25 (note 4) preset low 20 ns clear low 20 t su setup time data high 30 - ns (note 3)(note 5) data low 20 - t su setup time data high 35 - ns (note 5)(note 4) data low 25 - t h hold time (note 6) 0 - ns t a free air operating temperature 0 70 c
3 www.fairchildsemi.com DM74LS109a electrical characteristics over recommended operating free air temperature range (unless otherwise noted) note 7: all typicals are at v cc = 5v, t a = 25 c. note 8: not more than one output should be shorted at a time, and the duration should not exceed one second. for devices, with feedback from the outputs, where shorting the outputs to ground may cause the outputs to change logic state an equivalent test may be performed where v o = 2.125v with the minimum and maximum limits reduced by one half from their stated values. this is very useful when using automatic test equipment. note 9: i cc is measured with all outputs open, with clock grounded after setting the q and q outputs high in turn. switching characteristics at v cc = 5v and t a = 25 c symbol parameter conditions min typ max units (note 7) v i input clamp voltage v cc = min, i i = - 18 ma - 1.5 v v oh high level v cc = min, i oh = max 2.7 3.4 v output voltage v il = max, v ih = min v ol low level v cc = min, i ol = max 0.35 0.5 output voltage v il = max, v ih = min v i ol = 4 ma, v cc = min 0.25 0.4 i i input current @ max v cc = max j, k 0.1 input voltage v i = 7v clock 0.1 ma preset 0.2 clear 0.2 i ih high level v cc = max j,k 20 input current v i = 2.7v clock 20 m a preset 40 clear 40 i il low level v cc = max j, k - 0.4 input current v i = 0.4v clock - 0.4 ma preset - 0.8 clear - 0.8 i os short circuit output current v cc = max (note 8) - 20 - 100 ma i cc supply current v cc = max (note 9) 4 8 ma from (input) r l = 2 k w symbol parameter to (output) c l = 15 pf c l = 50 pf units minmaxminmax f max maximum clock frequency 25 20 mhz t plh propagation delay time clock to 25 35 ns low-to-high level output q or q t phl propagation delay time clock to 30 35 ns high-to-low level output q or q t plh propagation delay time clear 25 35 ns low-to-high level output to q t phl propagation delay time clear 30 35 ns high-to-low level output to q t plh propagation delay time preset 25 35 ns low-to-high level output to q t phl propagation delay time preset 30 35 ns high-to-low level output to q
www.fairchildsemi.com 4 DM74LS109a physical dimensions inches (millimeters) unless otherwise noted 16-lead small outline integrated circuit (soic), jedec ms-012, 0.150 narrow package number m16a
5 www.fairchildsemi.com DM74LS109a dual positive-edge-triggered j-k flip-flop with preset, clear, and complementary outputs physical dimensions inches (millimeters) unless otherwise noted (continued) 16-lead plastic dual-in-line package (pdip), jedec ms-001, 0.300 wide package number n16e fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fairchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchilds products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. a critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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